Computer, microcontroller and microprocessor systems use one or more clock oscillator circuits to provide timing reference signals. Conventional clock oscillator circuits using an external-based clock can be used to provide a clock signal. A precision timing component (i.e., crystal, ceramic resonator, etc.) that is external to the oscillator circuit is required in an external-based clock oscillator. The precision timing component supplies a reference frequency for the clock oscillator. Interfacing to the timing component requires one or two pins of the chip that the external-based clock oscillator circuit is on. The precision timing component adds to the cost of a system. The chip uses the reference frequency presented by the timing component or further tunes the frequency to match the data rate of incoming data or a multiple of the data rate. Phase Lock Loop (PLL) and/or Delay Lock Loop (DLL) circuits can be used for locking to or matching data rates. Locking to or matching data rates sometimes requires long data ‘training’ sequences. Schemes that use a local fixed reference frequency do some phase shifting or phase selection to sample incoming data since the external and internal clock rates differ.
Conventional Universal Serial Bus (USB) communication systems are PLL based, with an accurate local clock. The USB device can be compliant with the USB specification version 2.0 (published April 2000), which is hereby incorporated by reference in its entirety. USB version 2.0 host Full-speed communications packets include accurately spaced ‘Start Of Frame’ (SOF) packets that arrive periodically every 1 ms±0.05% (i.e., 1.000 ms+500 ns)(see USB specification version 2.0, sections 7.1.11 and 7.1.12).
A clock oscillator that takes advantage of the accurately spaced USB SOF packets to calibrate the frequency of the clock signal would be desirable.